There are such a lot of issues we approximate to make life easy. Wires, for instance, haven’t any resistance or different unusual results. Crystal oscillators output their precise frequency. However absolutely our mannequin of how a pc shops and hundreds reminiscence is correct, proper? You set knowledge in a specific location and, later, you are taking it out. The [FEX-Emu] builders have a distinct perspective. After you have caches and, maybe, a number of CPUs, it isn’t that simple.
The fundamental drawback is that this: if one CPU (or, extra precisely, bus grasp) writes to a location, will one other CPU have entry to the brand new worth? X86’s Whole Retailer Ordering mannequin provides programmers robust ensures about when hundreds and shops grow to be seen, whereas ARM intentionally makes use of a weaker reminiscence mannequin that allows significantly extra reordering for efficiency and effectivity.
An emulator can, in principle, compensate by translating atypical x86 reminiscence operations into ARM purchase/launch operations, however doing that for almost each reminiscence reference will be costly. Newer ARM extensions akin to LRCPC assist significantly, whereas Apple took a extra direct method by including an x86-compatible TSO mode to Apple Silicon. That lets atypical hundreds and shops behave the way in which translated x86 code expects with comparatively little overhead.
Issues get a lot uglier with unaligned accesses and atomic operations. X86 software program routinely performs accesses that ARM would contemplate badly aligned, and x86 offers surprisingly robust atomicity ensures inside a cache line. FEX generally has to catch alignment faults and dynamically patch translated code with limitations. Cut up-lock operations are worse nonetheless: some require excursions by the kernel and sign handlers and will be tons of or 1000’s of occasions slower than the traditional case. Qualcomm’s newer Oryon cores enhance issues by supporting coherent cache-line atomics, whereas Valve has shipped a Linux kernel optimization that handles some troublesome unaligned atomics straight.
There’s one other significantly nasty nook involving write-combined GPU reminiscence. PC video games steadily count on x86 ordering semantics whereas writing uncached buffers destined for a discrete GPU. ARM at the moment lacks a clear equal for a few of these shops, and FEX measured worst-case bandwidth greater than 800× slower, sufficient to cut back some video games to under 1 FPS. UMA methods fare significantly better as a result of drivers can usually substitute atypical cache-coherent reminiscence.
It’s a protracted article, however illustration of why trendy emulators are much less about translating directions and extra about reproducing many years of architectural assumptions that software program quietly relies upon upon. After all, not all emulators or processor recreations are this correct, and infrequently that’s adequate. However generally you want a recreation that’s actually cycle-accurate and behaves precisely like the unique.
